Floating-Point Accelerators for MicroBlaze EDK-Based Systems
Features
- Instant runtime reconfiguration through changing the content of a firmware program memory.
- Support for runtime re-programming of the accelerator firmware from MicroBlaze in parallel to accelerator computation.
- Substantial reduction of power per MFLOP by execution of hand-coded computing sequences under firmware control.
- Basic computing elements (BCEs) are provided as FSL pcores for EDK 9.1.02 (MicroBlaze 6.00.b) or EDK 10.1.02 (MicroBlaze 7.10.c) with PLB v4.6 bus.
- Compilation targets: standalone or petalinux.
- BCEs use pipelined single precision floating point (FP) cores and pipelined double precision floating point (DP) cores from the Xilinx Core Generator floating-point library version 3.0 or 4.0.
- BCEs work with single FP/DP data path or SIMD (x2, x4 and x8) FP/DP data paths.
- Each BCE includes a single PicoBlaze processor.
Do you want to know more?
Please contact us through this form or continue to read below. Other contacts are on the page with contact information.Basic Computing Element (BCE)
The basic computing element increases the level of design abstraction of FPGA designs. The element uses a combination of a simple CPU with a configurable pipelined datapath to implement basic floating-point vector and matrix operations. The function of the element can be changed through replacing the CPU program.
API compatibility
- ALL BCEs use an identical low-level MicroBlaze SW API
- All SIMD BCEs (SIMD x2, x4 or x8) are capable to act as a single-data-path BCE.
- Each BCE firmware includes a function that reports back information on BCE capabilities.
- Double precision API is similar to the single precision API.
- BCEs use an identical firmware for both precisions (FP or DP) of the corresponding accelerator pcore.
Availability and requirements
Base system
- CPU: MicroBlaze 6.00.b or MicroBlaze 7.10.c, FPU enabled, DDR/DDR2 SDRAM
- Communication: Xilinx UART Lite 115.2 Kbps, Xilinx Ethernet MAC Lite
- Compilation targets: standalone or petalinux
Tools
- Xilinx ISE 9.1.03/EDK 9.1.02. Required IP cores: MicroBlaze 6.00.b, MCH-OPB DDR controller, FP unit
- Xilinx ISE/EDK 10.1.02. Required IP cores: MicroBlaze 7.10.c, PLB v4.6 bus, MPMC 4.02.a controller, FP unit
Board compatibility
- Spartan-3E Starter Kit
- Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition
- Spartan-3AN Starter Kit
- XtremeDSP Starter Platform — Spartan-3A DSP 1800A Edition
- Virtex-4 ML402 SX XtremeDSP Evaluation Platform
- XtremeDSP Development Platform — Virtex-5 FPGA ML506 Edition
Linux compatibility
- PetaLogix PetaLinux v0.30-rc for the petalinux target. Installation image:
http://developer.petalogix.com/downloads/petalinux-v0.30-rc1.tar.gz
Licensing
- Evaluation license with a limited lifespan.
- Full license.
Number of used IP cores
| FSL pcore accelerator | FP/DP ADD | FP/DP MULT | FP/DP DIV |
| fp01_1x1 [mac, dot] | 1 | 1 | - |
| fp01_1x2 [mac, dot, dot2] | 2 | 2 | - |
| fp01_1x4 [mac, dot, dot4] | 4 | 4 | - |
| fp01_1x8 [mac, dot, dot8] | 8 | 8 | - |
| fp02_1x1 [mac, dot] | 1 | 1 | 1 |
| fp02_1x2 [mac, dot, dot2] | 2 | 2 | 1 |
| fp02_1x4 [mac, dot, dot4] | 4 | 4 | 1 |
| fp02_1x8 [mac, dot, dot8] | 8 | 8 | 1 |
| dp01_1x1 [mac, dot] | 1 | 1 | - |
| dp01_1x2 [mac, dot, dot2] | 2 | 2 | - |
| dp01_1x4 [mac, dot, dot4] | 4 | 4 | - |
| dp02_1x1 [mac, dot] | 1 | 1 | 1 |
| dp02_1x2 [mac, dot, dot2] | 2 | 2 | 1 |
| dp02_1x4 [mac, dot, dot4] | 4 | 4 | 1 |
Supported boards
| FSL pcore accelerator | S3E 500 | S3AN 700 | S3E 1600 | S3A DSP1800 |
ML402 (VSK) | ML506 |
| fp01_1x1 [mac, dot] |
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| fp01_1x2 [mac, dot, dot2] |
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| fp01_1x4 [mac, dot, dot2] |
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| fp01_1x8 [mac, dot, dot8] |
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| fp02_1x1 [mac, dot] |
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| fp02_1x2 [mac, dot, dot2] |
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| fp02_1x4 [mac, dot, dot4] |
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| fp02_1x8 [mac, dot, dot8] |
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| dp01_1x1 [mac, dot] |
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| dp01_1x2 [mac, dot, dot2] |
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| dp01_1x4 [mac, dot, dot4] |
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| dp02_1x1 [mac, dot] |
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| dp02_1x2 [mac, dot, dot2] |
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| dp02_1x4 [mac, dot, dot4] |
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