Roman Bartosinski
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Daněk Martin, Kadlec Jiří, Bartosinski Roman, Kohout Lukáš:
Increasing the Level of Abstraction in FPGA-based Designes
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International Conference on Field Programmable Logic and Applications
, Eds: Kebschull Udo,
International Conference on Field Programmable Logic and Applications,
(Heidelberg, DE, 08.09.2008-10.09.2008) (2008)
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Daněk Martin, Philippe J.-M., Bartosinski Roman, Honzík Petr, Gamrat Ch.:
Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures
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International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008
, Eds: Hornby Gregory S., Sekanina Lukáš, Haddow Pauline C.,
International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008,
(Praha, CZ, 22.09.2008-24.09.2008) (2008)
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Kadlec Jiří, Bartosinski Roman, Daněk Martin:
Accelerating MicroBlaze Floating Point Operations
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Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL)
, Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis,
International Conference on Field Programmable Logic and Applications. FPL 2007,
(Amsterdam, NL, 27.08.2007-29.08.2007) (2007)
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Bartosinski Roman, Hanzálek Z., Stružka P., Waszniowski L.:
Integrated Environment for Embedded Control Systems Design
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Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium,
21st IEEE International Parallel & Distributed Processing Symposium,
(Long Beach, US, 26.03.2007-30.03.2007) (2007)
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Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf:
Dynamic reconfiguration in FPGA-based SoC designs
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Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems, p. 129-136
, Eds: Takách G., Hlawiczka A., Sziraj J.,
University of West Hungary,
(Sopron 2005)
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IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./,
(Sopron, HU, 13.04.2005-16.04.2005) (2005)
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Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf:
Dynamic reconfiguration in FPGA-based SoC designs
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ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 35-38
, Eds: Bosschere K.,
HiPEAC Network of Excellence,
(Ghent 2005)
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ACACES 2005.,
(L'Aquila, IT, 26.07.2005) (2005)
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Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf:
Dynamic reconfiguration in FPGA-based SoC designs. Abstract
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FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 274
, Eds: Schmidt H., Wilton S.,
ACM,
(Monterey 2005)
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FPGA 2005 /13./,
(Monterey, US, 20.02.2005-22.02.2005) (2005)
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Bartosinski Roman, Stružka P., Waszniowski L.:
Peert-blockset for processor export and matlab/simuling integration
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Technical Computing Prague 2005 : 13th Annual Conference Proceedings, p. 1-8
, Eds: Moler C., Procházka A., Walden B.,
MATLAB 05. Technical Computing Prague 2005,
(Praha, CZ, 15.11.2005) (2005)
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Last modification:
03.09.2008