Profile
Our group focuses on research, development and implementation of advanced digital signal processing algorithms, mainly in the fields of adaptive control and audio processing. We build on our experience with statistics, namely with the Bayesian approach to system identification and modeling, as well as the relevant fields of linear algebra.
Our target platforms are Field Programmable Gate Arrays (FPGAs) and Digital Signal Processors (DSPs). We use Matlab/Simulink to specify, model and verify algorithms that we later convert and synthesize to HW. As such specialized solutions are likely to be used in embedded systems, we also research features that result in extremely fast execution, use small amount of memory, small chip area or low power consumption. We achieve this both through designing new or modifying existing DSP algorithms, and using architectural properties such as dynamic reconfiguration of FPGAs...
News
FET Conference 2009
Our group presented a poster on today's applications of logarithmic arithmetic, and demonstrated an architecture for an efficient implementation of flexible DSP architecture in FPGAs together with a software application for measuring characteristics of yeast colonies for biology at the FET Conference (FET09), organized jointly by the European Commission, the Czech Academy of Sciences and the Czech Technical University. Although the conference is over now, you can still visit our virtual booth here.
The FPL2009 Conference
Our department is involved in the organization of this year's FPL conference, the first and largest conference on field-programmable logic, held annually in Europe. FPL2009 will take place in Prague from August 31 till September 2. To see the call for papers and other details visit the FPL2009 web page.
ARTEMIS & ENIAC JTI Info-day 2nd March 09 in UTIA
OKO-ICT Branch Contact Organization prepared ARTEMIS & ENIAC Joint Technology Initiatives Call 2009 information workshop.
Presentations can be download
here.
PF2009
We would like to wish all our friends, colleagues, supporters and symphathizers a peaceful Christmas and all the best in 2009.
FPL2008 Conference
Our group will present a paper at the FPL2008 Conference. The talk will discuss an architecture with several levels of abstraction, suitable for designing complex digital circuits. The presentation will take place in Heidelberg on September 8.
COSINE2 Workshop on Embedded Systems Education & Training
The workshop will take place on Thursday June 5, 2008, following the ARTEMIS general assembly meeting in Athens on June 4. It will focus on exchanging views between academia and policy makers about the current challenges in embedded systems education and training (industrial needs; SME needs; market aspects). The participants will have an opportunity to present their experience, needs and views. The workshop is organized by the COSINE2 project. The contact person is Jiri Kadlec . More information can be found on the OKO-IST web pages.