ARTEMIS/ENIAC Joint Undertaking Information workshop
OKO-ICT Branch Contact Organization organizes ARTEMIS/ENIAC Joint Undertaking Information workshop. It will be held at Academy of Sciences, Narodni 3, Prague 1, room 205 on Friday 16th May 08. Speakers: Eric Schutz, Alun Foster (ARTEMIS Prezidium) and Jiri Kadlec (member Public Authority Board). Participation is free of charge. More information and registration form are on OKO-IST web pages
IP2007 Conference
Our group will present a novel emulation technique at the IP conference in Grenoble. The emulation technique allows to preserve structure of a circuit according to a target technology during fault emulation in FPGA. It also allows to emulate timing parameters of the circuit.
Regional Conference on Embedded and Ambient Systems
UTIA will be present at the Regional Conference on Embedded and Ambient Systems (RCEAS 2007) held in Budapest on November 22-24. Our first talk will describe the current situation of the Czech Republic in joining the Artemis programme, and the second talk will describe the UTIA strategy in embedded systems.
Winterschool: "Self-Organisation in Embedded Systems"
Our group has been invited to demonstrate our DSP platform for FPGA-based embedded systems at the SOES workshop held at Dagstuhl. See the official SOES webpage for more details.
Apple-CORE
Our group is involved in a new EU-FP7 project called Apple-CORE. The project will develop compilers, operating systems and execution platforms to support and evaluate a novel architecture paradigm that can exploit many-core computer systems to the end of silicon. For more information follow this link.
AMWAS Workshop
Our group presented a platform for digital signal processing in FPGA-based embedded systems at the Aether-Morpheus Workshop and Summer School in Paris. The platform provides extensions to the Xilinx EDK tool that implement efficient floating-point vector operations. The platform is based on a network of heterogenous reprogrammable worker units. Each unit contains several basic floating-point operations (e.g. ADD, MUL) that can be interconnected in several ways; each such configuration implements a basic vector operation (e.g. VADD, VMAC). The software configurability and reprogrammability increases reuse of the hardware function units, and reduces the complexity of the final data path.