Position: head of the department

Department: Signal Processing (ZS)

Research interests: Recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; Scalable floating point arithmetic for FPGA SoC designs

Phone: +420 26605 2216

Fax: +420 266052511

Address: Pod Vodárenskou věží 4, CZ-182 08, Praha 8, Czech Republic