Ing. Jiří Kadlec, CSc.
Position: head of the department
Research interests: Recursive system identification algorithms suitable for FPGA; rapid prototyping of advanced signal processing algorithms; Scalable floating point arithmetic for FPGA SoC designs
Publications at UTIA: list Email: 
Phone: +420 26605 2216
Fax: +420 266052511
Address: Pod Vodárenskou věží 4, CZ-182 08, Praha 8, Czech Republic
List of supervised Ph.D. students:
Responsible for information:
ZS Last modification:25.11.2009
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