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19 Mar 09 - 30 Oct 09
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department of Signal Processing, UTIA
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  • cze

News Profile
Expertise
  • Floating Point
    Accelerators
Presentations
EU R&D
Projects
  • AETHER
  • Apple-CORE
  • Past projects
National R&D
Projects
  • CAK 2
  • GIN
  • VLAM
  • XML_FED
  • Past projects
Support
Projects
  • COSINE 2
  • Idealist2011
  • OKO ICT
  • Past projects
IP Cores &
Other Results
Staff Contact
Useful Links
  • UTIA
  • AS CR

Results

  • HSLA version 3.0.0 evaluation package

  • Simulator of Physical Layer of the ADSL Modem

  • Adaptive Noise Canceller LS Lattice Demo

  • Accelerator for Cross Ambiguity Function for Modern Passive Coherent Locator Systems

  • Image Compression Algorithms

  • RCCOM - Toolbox for supporting communication with FPGA development boards from Matlab/Simulink

  • Corner detection

  • Accelerator for Computation ADSL Line Response

  • Implementation of Accelerators for Decoding Reed-Solomon and Convolution error-correcting code on FPGA

  • Adaptive Noise Canceller Migration Demo

  • Peripheral Controllers for Spartan3E Starter Kit Development Board

  • Floating Point Accelerators for MicroBlaze - Partial Runtime Reconfiguration

  • Petri dish evaluation demo using the Uni1P/DX64 acceleration board

  • RIPAC Frontend - Preparing blocks in Simulink

  • Application handbook for the Uni1P development board and for the DX64 modules

  • Fault Injection into Emulated ASIC Netlists Using Partial Runtime Reconfiguration of FPGA

  • RETAC Demo - Fault Emulator v2.0

  • Tool for Preparation of Emulation of Time-Annotated ASIC Netlists


Last mod: Fri, 09 Jan 2009 13:05:28 +0100
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